The invention relates generally to various aspects of a beamformer (BF) for an ultrasound system.
Current state-of-the-art beamformers (BFs) use digital custom integrated circuit (CIC) chips to perform the functions of the beamformer associated with the signals transmitted to and received from transducer elements of an ultrasound probe. A CIC chip performs signal processing on a matrix of input signals received from a number of the transducer elements. The transducer elements generate input signals when the transducer elements receive ultrasound echoes from a region of interest in response to an ultrasound scan pulse. The CIC chip combines the matrix of input signals into one or more BF receive beams. Each input signal is also referred to as an input or transducer channel. Conventional CIC chips may handle 64 or 128 or 256 transducer channels on one common chip. The CIC chip uses predetermined sets of delays to form each receive beam from the input signals.
A CIC chip is designed to use a different set of delays with the same set of input channels or input signals to obtain or form multiple receive beams. The multiple receive beams are associated with the ultrasound echoes from focal points along multiple scan lines for a given ultrasound pulse. In this case, the signals received from multiple transducer elements may be processed simultaneously into multiple receive beams, this process being referred to as multi-line acquisition (MLA). The simultaneous collecting and processing of echo information along multiple scan lines within the subject is referred to as multi-line acquisition (MLA). MLA allows multiple beams to be assembled or formed simultaneously. As the number of MLA beams increases, the CIC chip size (e.g. amount of circuitry) also increases. An alternative to increasing the CIC chip size is to reduce the number of receive inputs in the matrix of receive inputs when increasing the number of MLA beams to be processed by the CIC chip.
Conventional BF technology dedicates a given size CIC chip and its associated board to a particular MLA size or capability. For example, a system having MLA4 (e.g. simultaneously producing 4 receive beams or 4 multi-line acquisitions) would use a specially designed MLA4 CIC chip and specially designed boards for the MLA4 CIC chips. In order to upgrade an ultrasound system from MLA4 to, for example, MLA8 (e.g., simultaneously producing 8 receive beams or 8 multi-line acquisitions), entirely different dedicated CIC chips and CIC boards would be designed and customized for the MLA8 system. Hence, each CIC chip is customized to produce the receive beams needed from a particular matrix of input signals. As the number of receive beams increases, the internal circuitry of the CIC chip increases. With each increase in the number of receive beams to be produced, the number of duplicated circuits internal to the CIC chip increases, and the CIC chip becomes larger and larger.
Further, each newly designed CIC chip is masked in silicon which is an expensive nonrecurring engineering (NRE) cost. In the case of MLA8 or MLA16 (8 MLA beams or 16 MLA beams, correspondingly), the CIC chip may cost two to four times more than a CIC chip designed for MLA2 (2 MLA beams). Although lower tier MLA systems do not need and do not have the additional MLA capabilities of higher tier MLA systems, the lower tier MLA systems still bear a significant portion of the costs.
A seemingly obvious solution is to connect the analog-to-digital converter (ADC) output to multiple CICs. However conventional ADCs have a limited drive capability and most can not drive multiple CIC inputs. In addition, newer ADCs utilize source-synchronous LVDS (Low Voltage Differential Serial) Interfaces. These interface have a significant advantage with reduced I/O and power dissipation for the many ADCs and CICs. This leads to miniaturization with higher levels of integration, i.e. more channels per device. However this type of interface is inherently point-to-point. It typically can not drive multiple inputs without risk of data corruption.
A need exists for an improved beamformer architecture capable of being scalable between different MLA sizes using the latest, commercially available ADCs